Cadence and TSMC Partner on N16 mmWave RF Design Enablement to Accelerate Innovation in Mobile, 5G and Automotive Applications
Cadence Design Systems, Inc. CDNS announced today that Cadence® RFIC solutions support TSMC’s N16RF Design Reference Flow and Process Design Kit (PDK) to accelerate the next generation of mobile, 5G and automotive applications. The continued collaboration between Cadence and TSMC will enable joint customers to design solutions with Cadence for TSMC’s N16RF mmWave semiconductor technology.
Cadence RFIC solutions support Cadence Intelligent System Design™ Strategy that enables excellent System-on-Chip (SoC) design. To learn more about Cadence’s RFIC solutions, please visit http://www.cadence.com/go/rficsolutions.
Full RF design reference flow includes passive device modeling, block-level optimization, sensitive layout routing meshes, EM parasite sign-off, EM-IR analysis with custom passives, and self-heating. The reference flow includes several products optimized for TSMC’s N16RF mmWave process technology, including the Cadence Virtuoso® Schematic Editor, Virtuoso ADE Product Suite and integrated Specter® X simulator and HF option. In addition, the Flow features high-performance electromagnetic (EM) model generation using Cadence EMX® 3D planar solver for seamless back-annotation of S-parameter models in Golden Schematic and EM-IR analysis with self-heating with the Voltus™-Fi Custom Power Integrity Solution that allows automatic management of EM and RCX models for RF accurate results. The flow allows users to effectively manage corner simulations and achieve design robustness.
The EMX Planar 3D solver and Quantus™ Parasitic Extraction are integrated into the Virtuoso platform, enabling layered extraction of coupling effects and guaranteeing full EM-Parasitic Signoff. The Cadence RFIC Full Flow provides an efficient methodology to help engineers achieve design goals—performance, power efficiency, and…
